1. Field of the Invention
This invention relates generally to a wafer burn-in test circuit of a semiconductor memory device, and more particularly to a wafer burn-in test circuit which can provide a burn-in stress voltage by only using a prior word line driver without additional devices or circuits as a wafer burn-in test is performed.
2. Description of the Prior Art
Generally, a burn-in test of a semiconductor memory device is performed after wafer fabrication is completed so as to find a defective memory cell by supplying a high stress voltage (i.e., burn-in voltage) or to reduce a burn-in test time in an operation voltage range. At present, in a case where a conventional 16 Mb dynamic random access memory (DRAM), the burn-in test circuit is operated in accordance with a 1K or a 4K refresh option, wherein the 1K option is 16ea word line active and the 4K option is 4ea word line active. In a 16Mb DRAM composed of a 16K row.times.a 1k column, in order to supply the stress voltage to whole word lines, it is requires 1K times of a row active which is obtained by 16K over 16ea (i.e., 16ea row active in one time row active) In a similar manner, in a case of a 4K refresh, 4K times for the row active should be performed. Further, the total test time required for performing the burn-in test in whole cells of the 16Mb DRAM is 24 hours (i.e., one day) in 1K refresh or 96 hours (i.e., four days) in 4K refresh. Accordingly, the test cost is highly increased in proportion to these long test times.
In a conventional burn-in test, the wafer burn-in circuit is used so as to reduce both the burn-in test time and the cost thereof. In such a manner, a stress voltage is provided to gate oxide layers of whole word lines by turning on multi-word lines during a row active. The wafer burn-in test time according to such manner is reduced to 68.4 sec. At this stage, the time is obtained from the following equation. EQU T=cycle time.times.2(write/read).times.1m(16K row).times.1K column.times.stress number
(i.e., T=500 ns.times.2.times.1.times.1K.times.68,400 (s)=68.4 sec)
The operation of the conventional wafer burn-in test will now be described with reference to FIGS. 1 through 5.
FIG. 1 is a schematic diagram illustrating a row decoder circuit according to a conventional wafer burn-in test circuit.
In a normal mode of operation, a wafer burn-in signal wbi which is applied to a NOR gate is maintained at a logic low level, thereby driving all word lines selected by a row address.
On the other hand, in a wafer burn-in mode of operation, a wafer burn in signal wbi which is applied to a NOR gate is maintained at a logic high level, and transistors connected to an output node B coupled to the NOR gate is turned on. Next, the burn-in stress voltage VPP is supplied to a plurality of word lines WL0-WL3 by turning on all pass transistors coupled to a control voltage VG.
It is noted that the conventional wafer burn-in test circuit requires not only a pass transistors group controlled by the control voltage VG for applying the high stress voltage, but also a plurality of NOR gates for selectively driving a word line driver in accordance with receiving the wafer burn-in signal wbi therein.
Under these conditions, the number of the word lines is increased further, the number of the pass transistors group and NOR gates are more highly increased, and the word lines structure is highly integrated in the area of the semiconductor memory devices.
FIG. 2 is a circuit diagram illustrating a wafer burn-in signal generating circuit according to the conventional wafer burn-in circuit.
Referring to FIG. 2, in the wafer burn-in mode of operation, if a power voltage is applied to a wbi pad, the wafer burn-in signal wbi is an output signal of the wafer burn-in signal generating circuit and becomes the logic high level and is simultaneously inputted to input terminals shown FIGS. 1 and 3.
Accordingly, by the wafer burn-in signal wbi, the stress voltage can be simultaneously provided to whole word lines during the active cycle.
FIG. 3 is a circuit diagram illustrating a row address pre-decoder circuit according to the conventional wafer burn-in test circuit.
According to FIG. 3, in the wafer burn-in mode of operation, if the wafer burn-in signal wbi is the logic high level, all decoded row addresses ax23, ax23b, ax2b3, and ax2b3b become the logic low level to thereby input to an input terminal shown in FIG. 4.
FIG. 4 is a circuit diagram illustrating a row address pre-decoder driving signal generating circuit according to the conventional wafer burn-in test circuit.
With reference now to FIG. 4, an output signal xdpb of the row address pre-decoder driving signal generating circuit is maintained at the logic low level by a row address ax230:3 which is outputted from the row address pre-decoder circuit shown in FIG. 3. In the wafer burn-in mode of operation, both the row decoder inputs ax23, ax45, and ax67 are maintained at the logic low level and if the output signal xdpb of the row address pre-decoder driving signal generating circuit is also maintained at logic low level, then the node A coupled to an output terminal of an inverter and a node B coupled to an output terminal of a NAND gate are maintained at the logic low level.
Next, as described hereinbefore with reference to FIG. 1, the high stress voltage VPP for performing the burn-in test is supplied to the plurality of word lines WL0-WL3 by turning on the pass transistors coupled to the control voltage VG. FIG. 5 shows the timing operations in the conventional wafer burn-in test circuit.
As described, the conventional wafer burn-in test circuit should require the pass transistors group and the plurality of NOR gates for applying the high stress voltage VPP as illustrated in FIG. 1 so that the plurality of word lines is simultaneously driven during one active cycle. Accordingly, the word lines structure is highly integrated in the semiconductor memory chip and an entire size of the semiconductor memory chip is bigger.